1. Field of the Invention
This invention relates to an integrated circuit chip package and interconnection assembly. More particularly it relates to a multichip package which provides for exceptionally high density electrical interconnection between multiple chips in one package.
2. Material Art
In a system of integrated circuits, there are two primary factors that influence the speed by which the integrated circuits of the system are able to receive, process and transmit electrical signals. These factors are: (1) how cool the circuits can be maintained and (2) how fast electrical signals can be transferred between components or elements of the circuits. Heat slows the operational capability of IC chips. Low temperature is difficult to achieve with conventional IC chip packaging because the package itself prohibits direct contact of a cooling medium to the IC chip for heat removal. Speed of electrical signal transfer relates to length of the electrical signal paths, and has been limited by the inability to provide interconnect densities on a conventional printed circuit board that rival those achievable on the integrated circuit chips themselves. Typical interconnect metallization line widths on IC chips have dimensions less than 10 microns whereas line widths on high performance printed circuit boards are more on the order of 125 microns. Thus, even though IC chips continue to increase in density, conventional packaging at the chip and system level has not followed this density increase because of such fundamental limitations as minimum line width on printed circuit boards.
In response to this need for higher density interconnection between chips, the development of improved packaging concepts is of major importance. One fairly early concept is seen in Doelp, U.S. Pat. No. 3,374,537 where, as shown in FIG. 1, thin film petal-type interconnections 6 and 14 are provided on a transparent glass substrate 4. Interconnect 14 connects between chips 10 and interconnect 6 and provides input and output connections from chips 10 to external leads of the package.
Jarvela, U.S. Pat. No. 4,000,509 discloses a high density multichip package. As shown in FIGS. 2A and 2B, Jarvela provides a wafer carrier assembly 12 attached to a heat sink 16. The wafer carrier assembly generally consists of a circular silicon wafer 21 having signal and power distribution circuit networks formed thereon. Wafer 21 is attached to a molybdenum stiffener for mechanical strength, which is connected through thermal grease 20 to heat sink 16. The thermal grease improves thermal conductivity between the heat generating chips 23 and the outside of the package. A plurality of chips 23 are mounted on the wafer and electrically connected to the circuit networks on the wafer 21. However, the glass or other electrically insulating material of wafer 21 also provides undesired thermal insulation between chips 23 and the heat sink 16.